SPC-180N Series

  • Fast PCIe Interface
  • Unprecedented Time Resolution
  • Minimum Time Channel Width
    SPC-180N:       813 fs
    SPC-180NX:    405 fs
    SPC-180NXX: 203fs
  • Internal Timing Jitter (RMS) / IRF Width (FWHM)
    SPC-180N:       2.5 ps / 6.6 ps
    SPC-180NX:    1.6 ps / 3.5 ps
    SPC-180NXX: 1.1 ps/ 3 ps
  • Excellent Timing Stability
  • -NX and -NXX Versions Ideal for Ultra-Fast HPM (Hybrid) Detectors and Superconducting NbN Detectors
  • 12 MHz Saturated Count Rate
  • Precision Fluorescence Decay Recording
  • High-Resolution FLIM
  • Simultaneous FLIM/PLIM
  • Multi-Wavelength FLIM
  • Realtime FLIM and FCS Recording
  • Photon Correlation
  • Single-Molecule Spectroscopy
  • Free Instrument Software for Windows 8/10/11
  • Realtime Calculation of FLIM Images and FCS Curves
  • Realtime Calculation of Decay Curves from FLIM ROIs
  • Realtime Fit of FCS Curves
  • Link to SPCImage NG Data Analysis
  • Parallel Operation of Up to 4 Modules
  • Available as Multi-Module Package, e.g. SPC-182NX, SPC-183NX and SPC-184NX
SPC-18N Family TCSPC Module

The SPC-180N series modules have ultra-fast timing electronics equivalent to those of the SPC‑150N series. The modules are available in three versions with different time range and time resolution. The SPC-180N has a minimum time-channel width of 813 fs , the SPC-180NX of 405 fs , and the SPC-180NXX of 203 fs. The intrisic IRF widths are 6.6 ps, 3.5 ps, and 2.8 ps, the internal timing jitter 6.6 ps, 3.5 ps, and 1.1 ps, respectively. The -NX version, and, especially, the -NXX version have been designed for ultra-fast detectors, SSPDs and ultra-fast hybrid detectors.
All SPC-180N series modules have high-speed PCI-Express (PCIe) interfaces. The new interface achieves extremely high data transfer rates. With the SPC-180N series modules, bus saturation and FIFO overflow in fast FLIM applications are unlikely to occur. To further facilitate fast FLIM, the modules of the SPC-180N series have a fast counter in parallel to the TCSPC timing electronics. This allows the data acquisition software to build up FLIM images the intensity of which remains linear up to the highest count rates.

The bh SPC modules use a multi-dimensional TCSPC principle. The principle is an extension of the classic TCSPC process: A detector detects single photons of a periodic light signal. The TCSPC electronics measures the times of the photons within the signal (excitation) period, and builds up the distribution of the photons over the time of the signal period. The time resolution of the TCSPC process is much higher than the resolution of an analog recording with the same detector: The time of a photon pulse can be determined with a much higher precision than its width.

In extension of the classic process, the bh technique determines additional parameters of the photons, such as wavelength, point of origin within an image area, excitation wavelength, time from an external stimulation of the sample, time within an additional modulation period of the excitation light. The photon distribution is built up over the photon times in the signal period and one or several of these additional parameters. The results of this process are multi-wavelength fluorescence-decay data, fluorescence-lifetime images, multi-wavelength lifetime images, multi-excitation decay data or multi-excitation FLIM data, decay data or FLIM data of fast dynamic changes within a sample, or combined fluorescence / phosphorescence decay data or FLIM / PLIM data. Please see also 'The bh TCSPC Technique'.




Photon Channel



Constant Fraction Discriminator (CFD)

Discriminator Input Bandwidth

4 GHz

Time Resolution (FWHM/RMS, electr.)

6.6 ps / 2.5 ps

< 3.5 ps / 1.6 ps

< 3 ps / 1.1 ps

Variance in Time of IRF max. (RMS)

< 0.4 ps over 100 s

Optimum Input Voltage Range

-30 mV to -500 mV

Min. Input Pulse Width

200 ps


0 to -250 mV

Zero Cross Adjust

-100 mV to 100 mV

Syncronisation Channel



Constant Fraction Discriminator (CFD)

Discriminator Input Bandwidth

4 GHz

Optimum Input Voltage Range

-30 mV to -500 mV

Min. Input Pulse Width

200 ps


0 to -250 mV

Frequency Range

0 to 150 MHz

Frequency Divider

1, 2, 4

Zero Cross Adjust

-100 mV to 100 mV

Time-to-Amplitude Converters / ADCs



Ramp Generator / Biased Amplifier

TAC Range

50 ns to 5 µs

25 ns to 2.5 µs

12.5 ns to 50 ns

Biased Amplifier Gain

1 to 15

Biased Amplifier Offset (of TAC Range)

0 % to 50 %

Time Range incl. Biased Amplifier

3.3 ns to 5 µs

1.67 ns to 2.5 µs

0.834 ns to 50 ns

Min. Time Channel Width

813 fs

407 fs

203 fs

ADC Principle

50 ns Flash ADC with Error Correction

Diff. Nonlinerarity

< 0.5 % RMS, typ. < 1 % peak-peak

Data Acquisition

Histogram Mode


on-board multi-dim. histogramming process

Dead Time

80 ns, independent of computer speed

Saturated Count Rate

12 MHz

Max. Counts / Time Channel

16 bits

Overflow Control

none, stop, repeat and correct

Collection Time

0.1 µs to 100,000 s

Diplay Interval Time

10 ms to 100,000 s

Repeat Time

0.1 µs to 100,000 s

Sequencing Recording

Programmable Hardware Sequencer, unlimited recording by Memory swapping, in curve mode and scan mode

Syncronisation with Scanning

Pixel, Line and Frame from Scanning Device


7 bit, TTL

Experiment Trigger


Data Acquisition

FIFO / Parameter-Tag Mode


Time and wavelength tagging of individual photons and continuous writing to disk

Online Display

Decay functions, FCS, Cross-FCS, PCH MCS Traces

FCS Calculation

Multi-tau algorithm, online calculation and online fit

Number of Counts of Decay/ Waveform Recording


Dead Time

80 ns

Saturated Count Rate, Peak

12 MHz

Sustained Count Rate (Bus Transfer Limit)

typ. 5 MHz

Max. Counts / Time Channel (Counting Depth)


Output Data Format (ADC / Macrotime / Routing)

12 / 12 / 4

FIFO Buffer Capacity (Photons)

2 * 106

Macro Timer Resolution, Internal Clock

25 ns, 12 bit, overflows marked by MOTF entry in data stream

Input Macro Timer Resolution, Clock from Sync

10 ns to 100 ns, 12 bit, overflow marked by MOTF entry in data stream

Input Curve Control (external Routing)

4 bit, TTL

External Event Markers

4 bit, TTL

Input Count Enable Control

1 bit, TTL

Input Experiment Trigger


Data Acquisition

FIFO / Parameter-Tag Imaging Mode


Buildingup images from time- and wavelength tagged data

Online Display

up to 8 Images in different time and wavelength windows

Synchronisation with Scanner

via Frame Clock, Line Clock and Pixel Clock Pulses

Detector / Wavelength Channels

1 to 16

Image resolution (64-bit SPCM Software)


No. of Time Channels





No. of Pixels, 1 Detector Channel

4096 x 4096

2048 x 2048

1024 x 1024

512 x 512

No. of Pixels, 16 Detector Channels

1024 x 1024

512 x 512

256 x 256

128 x 128

Operation Environment


PC System

Windows 8 / 10, > 8 GB RAM, 64 bit operating system recommended

PC Interface


Power Consumption

approx. 12 W from +12 V


230 mm x 130 mm x 18 mm

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